1. Field of the Invention
The present invention relates to a composite semiconductor device for use in high speed switching, which has high breakdown voltage and large current capacity.
2. Description of the Background Art
FIG. 1 is a circuit diagram showing a cascode BiMOS (Bipolar and MOSFET combination) circuit as an example of a conventional power composite semiconductor device, wherein an NPN bipolar transistor Q1 and an N channel enhancement power MOS (metal-oxide-semiconductor) FET (field effect transistor) 2 are connected in series. As the bipolar transistor Q1, an element having a high breakdown voltage and large current capacity is used. An emitter of the bipolar transistor Q1 is connected to the drain of the power MOSFET 2. As the power MOSFET 2, an element having a low breakdown voltage of approximately 50V and large current capacity is used. A flywheel diode D1 for high frequency has a cathode connected to the collector C of the bipolar transistor Q1 and an anode connected to the source S of the power MOSFET 2. The bipolar transistor Q1 and the power MOSFET 2 are turned ON/OFF in response to levels of signals applied to the base B of the bipolar transistor Q1 and the gate G1 of the power MOSFET 2, so that the BiMOS circuit 1 is turned ON/OFF.
In the operation of the BiMOS circuit 1 shown in FIG. 1, positive and ground potentials are applied to the collector C of the bipolar transistor Q1 and the source S of the power MOSFET 2, respectively. When positive voltages are applied to the base B of the bipolar transistor Q1 and the gate G1 of the power MOSFET 2, both the transistors Q1 and 2 are turned ON and thus the BiMOS circuit 1 is turned ON. If the base B of the bipolar transistor Q1 is so biased that the BiMOS circuit 1 can be turned ON in response to only the signal to the gate G1 of the power MOSFET 2, the turn ON time of the BiMOS circuit 1 depends on only the turn ON time of the power MOSFET 2. In such a case, the tune ON time of the BiMOS circuit I can be extremely decreased.
To turn OFF the BiMOS circuit I, the positive voltages applied to the base B of the bipolar transistor Q1 and the gate G1 of the power MOSFET 2 are removed. In a turn OFF transition, the power MOSFET 2 is turned OFF prior to the turn OFF of the bipolar transistor Q1. As a result, the emitter of the bipolar transistor Q1 becomes a cut off state, so that residual carriers in the collector of the bipolar transistor Q1 are discharged through the base B of the bipolar transistor Q1. Thus, a breakdown voltage becomes equal to the emitter-open collector-to-base maximum voltage V.sub.CBO of the bipolar transistor Q1 due to the emitter cut off state of the bipolar transistor Q1 in the turn OFF transition. Thus, a circuit having a breakdown voltage higher than the ordinary breakdown voltage, i.e., base-open collector-to-emitter maximum voltage V.sub.CEO, of the bipolar transistor Q1 can be implemented.
In the BiMOS circuit 1 shown in FIG. 1, the bipolar transistor Q1 is used in a single stage structure because of high speed sWitching, and hence the current amplification factor thereof is small. Therefore, it is necessary to increase the capacity of a base driving circuit of the bipolar transistor Q1 to supply a large base current to the bipolar transistor Q1, in order to conduct a large current through the BiMOS circuit This results in the increase of power consumption. Further, the ON state resistance of the bipolar transistor Q1 is relatively large, and hence the power consumption of the bipolar transistor Q1 is disadvantageously large in the ON state of the BiMOS circuit 1.
FIG. 2 is a circuit diagram showing another conventional cascode BiMOS circuit which includes an N channel enhancement power MOSFET 3 for driving a bipolar transistor Q1 in FGT (FET gated transistor) structure and a zener diode ZD1 for rapidly discharging residual carriers in the collector of the bipolar transistor Q1 upon the emitter cut off state of the bipolar transistor Q1. The zener diode ZD1 has an anode connected to the source S of a power MOSFET 2 and a cathode connected to the base B of the bipolar transistor Q1. The zener diode ZD1 has a zener voltage of several volts. The power MOSFET 3 has a gate connected to the gate G1 of the power MOSFET 2, a drain connected to the collector C of the bipolar transistor Q1 and a source connected to the base B of the bipolar transistor Q1. As the power MOSFET 3, an element of the type of high breakdown voltage and middle current capacity is used. Other structures are the same as those of the circuit shown in FIG. 1.
In the operation of the BiMOS circuit 1 shown in FIG. 2, positive and ground potentials are applied to the collector C of the bipolar transistor Q1 and the source S of the power MOSFET 2, respectively, as is similar to the circuit of FIG. 1. When a positive voltage is applied to the gate G1, the power MOSFETs 2 and 3 are first turned ON. A base current is supplied to the base of the bipolar transistor Q1 through the power MOSFET 3, to turn ON the bipolar transistor Q1. Thus, the BiMOS circuit 1 is turned ON.
To turn OFF the BiMOS circuit I, the positive voltage applied to the gate G1 is removed. The power MOSFETs 2 and S are responsively turned OFF. and thus the bipolar transistor Q1 enters an emitter cut off state. Residual carriers in the collector of the bipolar transistor Q1 are discharged to the source S through the base B of the bipolar transistor Q1 and the zener diode ZD1 in a short period of time of several .mu.s. As a result, the bipolar transistor Q1 is rapidly turned OFF. and hence the turn OFF time of the BiMOS circuit approaches that of the power MOSFET 2, to enable high speed switching.
In the circuit shown in FIG. 2, it is required to sufficiently increase the capacity of the power MOSFET 3 serving as a base driving circuit for the bipolar transistor Q1, for the same reason as in the circuit shown in FIG. 1. Further, power consumption is disadvantageously increased due to the ON state resistance of the bipolar transistor Q1 as is similar to the circuit of FIG. 1.
FIG. 3 is a circuit diagram showing still another conventional cascade BiMOS circuit disclosed in Electrical Society Technical Bulletin Part II, No. 249, "Trend of Self-Suppressing Type Power Semiconductor Device", p.60, June 1987. Referring to FIG. 3, a flywheel diode D1 is connected between the source and drain of a power MOSFET 2. A current transformer 4 is interposed on the line of a collector side of a bipolar transistor Q1 and has one end connected to the source S of the power MOSFET 2 and the other end connected to the base B of the bipolar transistor Q1 through a diode D3. A capacitor Cl is connected between the base B of the bipolar transistor Q1 and the source S of the power MOSFET 2. The collector of the bipolar transistor Q1 is connected to the base B of the bipolar transistor Q1 through a diode D4 and a resistor R. Other structures are the same as those of the circuit shown in FIG. 2.
In the operation of the circuit shown in FIG. 3, positive and ground potentials are applied to the collector C and the source S, respectively. When both the bipolar transistor Q1 and the power MOFET 2 are in an OFF state, the capacitor C1 is charged to the zener voltage of the zener diode ZD1. Upon application of a positive voltage to the gate G1 of the power MOSFET 2, the power MOSFET 2 is turned ON to lower the emitter voltage of the bipolar transistor Q1. When the base-to-emitter voltage of the bipolar transistor Q1 becomes larger than a predetermined value, the bipolar transistor Q1 is turned ON so that a collector current begins to flow. The current transformer 4 responsively induces a current which is in turn supplied to the base B of the bipolar transistor Q1 through the diode D3. Once the collector current beings to flow through the bipolar transistor Q1, the current transformer 4 continues to stably supply a base driving current to the base B of the bipolar transistor Q1. Thus, a BiMOS circuit 1 is turned ON.
When a negative voltage is applied to the gate G1 of the power MOSFET 2, the power MOSFET 2 is turned OFF. As a result, the bipolar transistor Q1 enters an emitter cut off state. Therefore, residual carriers in the collector of the bipolar transistor Q1 are discharged through the case B of the bipolar transistor Q1 and the zener diode ZD1, as is similar to the circuit shown in FIG. 2. Thus, the BiMOS circuit 1 is rapidly turned OFF.
The circuit shown in FIG. 3 has the bipolar transistor Q1 of a signal stage structure as is similar to the circuit shown in FIG. 1. Therefor, a base driving circuit is complicated as shown in FIG. 3, to supply a sufficiently large base current to the bipolar transistor Q1 in order to conduct a large current from the collector C of the bipolar transistor Q1 to the source S of the power MOSFET 2. Power consumption is disadvantageously increased because of the large capacity of the base driving circuit. Further, a circuit area for the base driving circuit is disadvantageously increased due to the complication of the base driving circuit, to increase a cost.